Philips Semiconductors
PCF8594C-2
512 × 8-bit CMOS EEPROM with I 2 C-bus interface
7. Device addressing
Table 5:
Device address code
Selection
Device code
Chip Enable
R/W
Bit
Device
b7 [1]
1
b6
0
b5
1
b4
0
b3
A2
b2
A1
b1
A0
b0
R/W
[1]
The Most Signi?cant Bit (MSB) ‘b7’ is sent ?rst.
A2 and A1 are hardware selectable pins and A0 is software selectable pin.
A system could have up to four PCF8594C-2 devices on the same I 2 C-bus,
equivalent to a 16 kbit EEPROM or 4 devices of 512 bytes of memory.
A0 selects the lower (logic level ‘0’) or the higher (logic level ‘1’) 256-byte page on the
selected device. The device is selected by bits A2 and A1. Figure 3 shows the various
address and page combinations.
PCF8594C-2
I 2 C-BUS
DEVICE 1
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
A2
0
0
A1
0
0
A0
1
0
PCF8594C-2
DEVICE 2
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
0
0
1
1
1
0
PCF8594C-2
DEVICE 3
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
1
1
0
0
1
0
PCF8594C-2
DEVICE 4
HIGHER 256-BYTE PAGE
LOWER 256-BYTE PAGE
1
1
1
1
1
0
002aaa260
Fig 3. Device addressing.
9397 750 14221
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 05 — 25 October 2004
5 of 21
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